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19-1631; Rev 0a; 8/01
2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC
General Description
The MAX3876 is a compact, low-power clock recovery and data retiming IC for 2.488Gbps SDH/SONET applications. The fully integrated phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The data is retimed by the recovered clock. Differential CML outputs are provided for both clock and data signals, and an additional 2.488Gbps serial input is available for system loopback diagnostic testing. The device also includes a TTL-compatible loss-of-lock (LOL) monitor. The MAX3876 is designed for both section-regenerator and terminal-receiver applications in OC-48/STM-16 transmission systems. Its jitter performance exceeds all of the SONET/SDH specifications. This device operates from a +3.3V or +5.0V single supply over a -40C to +85C temperature range. Power consumption is typically only 445mW with a +3.3V supply. The MAX3876 is available in a 32-pin TQFP package as well as in die form.
Features
o Exceeds ANSI, ITU, and Bellcore SONET/SDH Regenerator Specifications o 440mW Power Dissipation (at +3.3V) o Clock Jitter Generation: 3.7mUIRMS o +3.3V or +5V Single Power Supply o Fully Integrated Clock Recovery and Data Retiming o Additional High-Speed Input Facilitates System Loopback Diagnostic Testing o Tolerates >2500 Consecutive Identical Digits o Loss-of-Lock Indicator o Differential CML Data and Clock Outputs
MAX3876
Applications
SDH/SONET Receivers and Regenerators Add/Drop Multiplexers Digital Cross-Connects 2.488Gbps ATM Receiver Digital Video Transmission SDH/SONET Test Equipment Intrarack/Subrack Interconnects
PART MAX3876EHJ MAX3876E/D
Ordering Information
TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 32 TQFP Dice*
*Dice are designed to operate over this range, but are tested and guaranteed at TA = +25C only. Contact factory for availability. Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V 0.01F VCC FILT PHOTODIODE 0.01F IN VCC OUT+ SDI+ SDO+ SDOLOL +3.3V TTL +3.3V
MAX3866
PREAMPLIFIER OUTSDISLBI+ SLBISIS FIL+ FILSCLKO+ SCLKO-
MAX3876
MAX3831 4:1/1:4 TRANSCEIVER
SYSTEM LOOPBACK
TTL
1F
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC MAX3876
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +7.0V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ...........(VCC - 0.5V) to (VCC + 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............11mA CML Output Current Levels (SDO+, SDO-, SCLKO+, SCLKO-) ................................22mA Voltage at LOL, SIS, FIL+, FIL-...................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) 32-Pin TQFP (derate 16.1mW/C above +85C).............1.0W Operating Temperature Range MAX3876EHJ..................................................-40C to +85C Operating Junction Temperature Range (die) ..-55C to +150C Storage Temperature Range .............................-60C to +160C Processing Temperature (die) .........................................+400C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at +3.3V and TA = +25C.) (Note 1) PARAMETER Supply Current Input Common-Mode Voltage Differential Input Voltage (SDI, SLBI) Single-Ended Input Voltage (SDI, SLBI) Input Termination to VCC (SDI, SLBI) CML Differential Output Voltage Swing Differential Output Impedance CML Output Common-Mode Voltage TTL Input High Voltage (SIS) TTL Input Low Voltage (SIS) TTL Input Current (SIS) TTL Output High Voltage (LOL) TTL Output Low Voltage (LOL) VOH VOL VIH VIL -10 2.4 RL = 50 to VCC 2.0 0.8 +10 VCC 0.4 SYMBOL ICC VCM VID VIS RIN RL = 50 to VCC TA = 0C to +85C TA = -40C 640 580 85 DC-coupled Figure 1, DC-coupled Figure 1, AC-coupled CONDITIONS Excluding CML output termination VCC - 0.25 50 50 VCC - 0.4 48 800 800 100 VCC - 0.2 1000 1000 115 1000 1600 VCC + 0.4 MIN TYP 135 MAX 167 UNITS mA V mVp-p V mVp-p V V V A V V
VCC + 0.4V 800mV VCC 25mV
tCK
VCC - 0.4V VCC
(a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL)
25mV
SCLKO+ tCK-Q SDO
500mV VCC - 0.25V
VCC - 0.5V
(b) DC-COUPLED SINGLE-ENDED CML INPUT
Figure 1. Input Amplitude 2
Figure 2. Output Clock-to-Q Delay
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at +3.3V and TA = +25C.) (Note 2) PARAMETER Serial Output Clock Rate Clock-to-Q Delay Jitter Peaking Jitter Transfer Bandwidth JP JBW f = 70kHz (Note 3) Jitter Tolerance f = 100kHz f = 1MHz f = 10MHz Jitter Generation Clock Output Edge Speed Data Output Edge Speed Tolerated Consecutive Identical Digits Input Return Loss (SDI, SLBI) 100kHz to 2.5GHz 2.5GHz to 4.0GHz JGEN Jitter BW = 12kHz to 20MHz 20% to 80% 20% to 80% 2.1 1.76 0.41 0.32 Figure 2 f 2MHz 110 0.03 1.4 4.4 3.32 0.74 0.51 3.7 19.2 75 95 2500 17 15 6.2 61.0 mUIRMS mUIp-p ps ps Bits dB UIp-p SYMBOL CONDITIONS MIN TYP 2.488 290 0.1 2.0 MAX UNITS GHz ps dB MHz
MAX3876
Note 1: Dice are tested at TA = +25C only. Note 2: AC characteristics are guaranteed by design and characterization. Note 3: At jitter frequencies < 70kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications.
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
RECOVERED DATA AND CLOCK (DIFFERENTIAL OUTPUT)
MAX3876 toc1
RECOVERED CLOCK JITTER
MAX3876 toc2
JITTER TOLERANCE
MAX3876 toc03
223-1 PATTERN VIN = 50mVp-p
TA = +25C
DATA
PRBS = 223-1 VIN = 50mVp-p WIDEBAND JITTER = 3.94psRMS
10
INPUT JITTER (UIp-p)
200mV/div
50mV/div
1 BELLCORE MASK
CLOCK
PRBS = 223 - 1 50mVp-p INPUT 0.1 100ps/div 10ps/div 10k 100k 1M 10M JITTER FREQUENCY (kHz)
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC MAX3876
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
JITTER TOLERANCE vs. INPUT AMPLITUDE
JITTER FREQUENCY = 1MHz 0.8 JITTER TOLERANCE (UIp-p) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 10 100 INPUT SIGNAL AMPLITUDE (mVp-p) 1000 TA = +85C PRBS = 223 - 1 -2.5 PRBS = 223 - 1 -3.0 1k 10k 100k 1M 10M JITTER FREQUENCY (Hz) PRBS = 223 - 1 10-10 8.8 8.9 9.0 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 INPUT SIGNAL AMPLITUDE (mVp-p) JITTER FREQUENCY = 5MHz
MAX3876 toc04
JITTER TRANSFER
MAX3876 toc05
BIT ERROR RATE vs. INPUT AMPLITUDE
MAX3876 toc06
0.9
0.5 0 JITTER TRANSFER (dB) -0.5 -1.0 -1.5 -2.0 BELLCORE MASK
10-5
10-6 BIT ERROR RATE 10-7 10-8 10-9
JITTER TOLERANCE vs. PULSE-WIDTH DISTORTION
100kHz PRBS = 223 - 1 100mVp-p INPUT
MAX3876 toc07
SUPPLY CURRENT vs. TEMPERATURE
155 SUPPLY CURRENT (mA) 150 VCC = 5.0V 145 140 135 130 VCC = 3.0V
MAX3876 toc08
10
160
JITTER TOLERANCE (UI)
1MHz 1.0
10MHz 0.1 0 0.05 0.10 0.15 0.20 0.25 PULSE-WIDTH DISTORTION (UI)
125 120 -50 -25 0 25 50 75 100 AMBIENT TEMPERATURE (C)
Pin Description
PIN 1, 2, 8, 9, 10, 16, 26, 29, 32 3, 6, 11, 14, 15, 17, 20, 21, 24, 27, 28 4 5 7 12 13 18 NAME GND Supply Ground FUNCTION
VCC SDI+ SDISIS SLBI+ SLBISCLKO-
Positive Supply Voltage Positive Data Input. 2.488Gbps serial-data stream. Negative Data Input. 2.488Gbps serial-data stream. Signal Input Selection, TTL. Low for normal data input. High for system loopback input. Positive System Loopback Input. 2.488Gbps serial-data stream. Negative System Loopback Input. 2.488Gbps serial-data stream. Negative Serial Clock Output, CML, 2.488GHz. SDO- is clocked out on the falling edge of SCLKO-.
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC
Pin Description (continued)
PIN 19 22 23 25 30 31 NAME SCLKO+ SDOSDO+ LOL FILFIL+ Negative Data Output, CML, 2.488Gbps Positive Data Output, CML, 2.488Gbps Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10k pull-up resistor) Negative Filter Input. PLL loop filter connection. Connect a 1.0F capacitor between FIL+ and FIL-. Positive Filter Input. PLL loop filter connection. Connect a 1.0F capacitor between FIL+ and FIL-. FUNCTION Positive Serial Clock Output, CML, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+.
MAX3876
SIS
FIL+
FIL-
SDO+ SDI+ AMP SDIMUX SLBI+ AMP SLBILOL TTL PHASE AND FREQUENCY DETECTOR LOOP FILTER I VCO Q CML SCLKO+ SCLKOD CK Q CML SDO-
MAX3876
Figure 3. Functional Diagram
Detailed Description
The MAX3876 consists of a fully integrated phaselocked loop (PLL), input amplifier, data retiming block, and CML output buffer (Figure 3). The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). This device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques.
up to 1000mVp-p. With AC-coupling, differential input signal amplitudes can be increased to a maximum of 1600mVp-p. The bit error rate is better than 1 * 10-10 for input signals as small as 10mVp-p, though the jitter tolerance performance will be degraded. For interfacing with PECL signal levels, see Applications Information.
Phase Detector
The phase detector incorporated in the MAX3876 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming.
Input Amplifier
Input amplifiers are implemented for both the main data and system loopback inputs. These amplifiers accept DC-coupled differential input amplitudes from 50mVp-p
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC MAX3876
Frequency Detector
The digital frequency detector (FD) aids frequency acquisition during start-up conditions. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on the rising edge of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is completely eliminated by this digital frequency detector.
HO(j2f) (dB)
OPEN-LOOP GAIN
CF = 1.0F fZ = 2.6kHz
CF = 0.1F fZ = 26kHz
Loop Filter and VCO
The phase detector and frequency detector outputs are summed into the loop filter. An external capacitor, CF, is required to set the PLL damping ratio. See Design Procedure for guidelines on selecting this capacitor. The loop filter output controls the on-chip LC VCO running at 2.488GHz. The VCO provides low-phase noise and is trimmed to the correct frequency. Clock jitter generation is typically 1.5psRMS within a jitter bandwidth of 12kHz to 20MHz.
1 10 100 1000
f (kHz)
Figure 4. Open-Loop Transfer Function
H(j2f) (dB) CF = 0.1F 0 CLOSED-LOOP GAIN -3 CF = 1.0F
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is incorporated in the MAX3876 frequency detector. A loss-of-lock condition is signaled immediately with a TTL low. When the PLL is frequency locked, LOL switches to TTL high in approximately 800ns. Note: The LOL monitor is valid only when a data stream is present on the inputs to the MAX3876. As a result, LOL does not detect a loss-of-power condition due to loss of the incoming signal.
f (kHz) 1 10 100 1000
Figure 5. Closed-Loop Transfer Function
Design Procedure
Setting the Loop Filter
The MAX3876 is designed for both regenerator and receiver applications. Its fully integrated PLL is a classic second-order feedback system, with a loop bandwidth (fL) fixed at 1.5MHz. The external capacitor, CF, can be adjusted to set the loop damping. Figures 4 and 5 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CF, and can be approximated according to: fz = 1 2 60 CF For an overdamped system (fZ/fL) < 0.25, the jitter peaking (MP) of a second-order system can be approximated by: f MP = 20log 1+ Z fL For example, using CF = 0.1F results in a jitter peaking of 0.2dB. Reducing CF below 0.01F may result in PLL instability. The recommended value for CF is 1.0F to guarantee a maximum jitter peaking of less than 0.1dB. CF must be a low TC, high-quality capacitor of type X7R or better.
()
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC
Input and Output Terminations
The MAX3876's digital outputs (SDO+, SDO-, SCLKO+, SCLKO-) are internally terminated with 50 to V CC (Figure 6). See the DC Electrical Characteristics for signal swing and common-mode voltage levels. To ensure best performance, the differential outputs must have balanced loads. The input termination can be driven differentially or can be driven single-ended by externally biasing SDI- or SLBI- to the center of the voltage swing.
PECL Input Levels
When interfacing with differential PECL input levels, it is important to attenuate the signal while still maintaining 50 termination (Figure 7). AC-coupling is also required to maintain the input common-mode level.
MAX3876
Layout
The MAX3876's performance can be significantly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the data and clock signals. Power-supply decoupling should be placed as close to VCC as possible. Take care to isolate the input from the output signals to reduce feedthrough.
Jitter Tolerance and Input Sensitivity Trade-Offs
When the received data amplitude is higher than 50mVp-p, the MAX3876 provides a typical jitter tolerance of 0.51UI at jitter frequencies greater than 10MHz. The SDH/SONET jitter tolerance specification is 0.15UI, leaving a jitter allowance of 0.36UI for receiver preamplifier and postamplifier design. The BER is better than 1 * 10-10 for input signals greater than 10mVp-p. At this input level, jitter tolerance will be degraded but will still be above the SDH/SONET requirement. The user can make a trade-off between jitter tolerance and input sensitivity according to the specific application. See the Typical Operating Characteristics for Jitter Tolerance and BER vs. Input Amplitude graphs.
VCC
50
50 SDO+ SDO-
Jitter Tolerance vs. Pulse-Width Distortion
The MAX3876 can typically tolerate up to 0.20UI of pulse-width distortion (PWD) and still exceed ITU and Bellcore specifications for sinusoidal jitter tolerance. Refer to the Typical Operating Characteristics for Jitter Tolerance and PWD vs. Jitter Frequency graphs.
MAX3876
Figure 6. CML Outputs
Applications Information
Consecutive Identical Digits (CIDs)
The MAX3876 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER of 1 * 10-10. The CID tolerance is tested using a 213 - 1 PRBS, substituting a long run of zeros to simulate the worst case. A CID tolerance of 2500 bits is typical.
System Loopback
The MAX3876 is designed to allow system loopback testing. The user can connect a serializer output in a transceiver directly to the SLBI+ and SLBI- inputs of the MAX3876 for system diagnostics. To select the SLBI inputs, apply a TTL logic high to the SIS pin.
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC MAX3876
VCC VCC = 3.3V 3.3V 0.1F PECL LEVELS RT* 100 0.1F 25 SDIZIN = 50 PECL OUTPUT 82 3.3V 226 243 SDIZIN = 50 82 VCC = 3.3V
25
SDI+ ZIN = 50
226 243 SDI+ ZIN = 50
RT*
MAX3876
MAX3876
*SELECT RT SUCH THAT THE CORRECT PECL COMMON-MODE LEVEL IS ACHIEVED (TYPICAL PECL OUTPUT CURRENT = 14mA).
Figure 7. PECL-to-CML Interface
Figure 8. Direct Coupling of a PECL Output into the MAX3876
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC
Pin Configuration
TOP VIEW
GND GND GND FIL+ LOL FILVCC VCC
Chip Topography
FIL+ GND GND VCC VCC LOL FILGND
MAX3876
32 GND GND VCC SDI+ SDIVCC SIS GND 1 2 3 4 5 6 7 8 9 GND
31
30
29
28
27
26
25 24 VCC 23 SDO+ 22 SDO21 VCC
VCC GND GND VCC SDI+ SDIVCC SIS GND SDO+ SDOVCC 0.072" VCC (1.828mm) SCLKO+ SCLKOVCC GND
MAX3876
20 VCC 19 SCLKO+ 18 SCLKO17 VCC
10 GND
11 VCC
12 SLBI+
13 SLBI-
14 VCC
15 VCC
16 GND
GND
SLBI+ VCC VCC VCC SLBI- N.C. N.C. 0.071" (1.803mm)
TQFP
TRANSISTOR COUNT: 1334 SUBSTRATE CONNECTED TO GROUND
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2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC MAX3876
Package Information
32L,TQFP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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